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MTP15N06VL的技术资料
MTP15N06VL的技术资料
来源：
汕头市创世纪电子发展有限公司
发布日期：2009-4-16 15:50:25
MTP15N06VL的产品特征：
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
以上信息由『维库电子开发网』（www.weeqoo.com）整理。
MTP15N06VL的技术参数：
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
资料整理：维库电子开发网（www.weeqoo.com），全球最大的芯片PDF资料下载基地。
MTP15N06VL的产品描述：
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
以上信息由『维库电子开发网』（www.weeqoo.com）整理。
MTP15N06VL的技术参数：
|
Rating |
Symbol |
Value |
Unit |
| Drain–to–Source Voltage |
VDSS |
60 |
Vdc |
| Drain–to–Gate Voltage (RGS = 1.0 MΩ) |
VDGR |
60 |
Vdc |
| Gate–to–Source Voltage — Continuous — Non–Repetitive (tp ≤10 ms) |
VGS VGSM |
± 15 ± 20 |
Vdc VPK |
| Drain Current — Continuous — Continuous@ 100°C — Single Pulse (tp ≤ 10 μs) |
ID ID IDM |
15 12 53 |
Adc Apk |
| Total Power Dissipation Derate above 25°C |
PD |
60 0.40 |
Watts W/°C |
| Operating and Storage Temperature Range |
TJ, Tstg |
–55 to 175 |
°C |
| Single Pulse Drain–to–Source Avalanche Energy TJ = 25°C (VDD =25 Vdc, VGS = 5.0Vdc, PEAK IL =15 Apk, L =1.0μH, RG = 25Ω) |
EAS |
113 |
mJ |
| Thermal Resistance — Junction to Case — Junction to Ambient |
RθJC RθJA |
2.5 62.5 |
°C/W |
| Maximum Lead Temperature for Soldering Purposes, 1/8"from Case for 10 seconds |
TL |
260 |
°C |
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
资料整理：维库电子开发网（www.weeqoo.com），全球最大的芯片PDF资料下载基地。
MTP15N06VL的产品描述：
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E–FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
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