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MTB2P50E的技术资料
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
以上信息由『维库电子开发网』（www.weeqoo.com）整理。
MTB2P50E的技术参数：
| Rating |
Symbol |
Value |
Unit |
| Drain–to–Source Voltage |
VDSS |
500 |
Vdc |
| Drain–to–Gate Voltage (RGS = 1.0 MΩ) |
VDGR |
500 |
Vdc |
| Gate–to–Source Voltage — Continuous — Non–Repetitive (tp ≤ 10 ms) |
VGS VGSM |
± 20 ± 40 |
Vdc Vpk |
| Drain Current — Continuous — Continuous @ 100℃ — Single Pulse (tp ≤ 10 μs) |
ID ID IDM |
2.0 1.6 6.0 |
Adc Apk |
| Total Power Dissipation @ 25℃ Derate above 25℃ Total Power Dissipation @ TA = 25℃ (1) |
PD |
75 0.6 2.5 |
Watts W/℃ Watts |
| Operating and Storage Temperature Range |
TJ, Tstg |
– 55 to 150 |
℃ |
| Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25℃ (VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 Ω) |
EAS |
80 |
mJ |
| Thermal Resistance — Junction to Case — Junction to Ambient — Junction to Ambient (1) |
RθJC RθJA RθJA |
1.67 62.5 50 |
℃/W |
| Maximum Lead Temperature for Soldering Purposes, 1/8"from case for 10 seconds |
TL |
260 |
℃ |
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
资料整理：维库电子开发网（www.weeqoo.com），的芯片PDF资料基地。
MTB2P50E的产品描述：
The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.