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MTB30N06VL的技术资料
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETs
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number
以上信息由『维库电子开发网』（www.weeqoo.com）整理。
MTB30N06VL的技术参数：
| Rating |
Symbol |
Value |
Unit |
| Drain–to–Source Voltage |
VDSS |
60 |
Vdc |
| Drain–to–Gate Voltage (RGS = 1.0 MΩ) |
VDGR |
60 |
Vdc |
| Gate–to–Source Voltage — Continuous — Non–Repetitive (tp ≤ 10 ms) |
VGS VGSM |
±15 ±20 |
Vdc Vpk |
| Drain Current — Continuous — Continuous @ 100℃ — Single Pulse (tp ≤ 10 μs) |
ID ID IDM |
30 20 105 |
Adc Apk |
| Total Power Dissipation @ 25℃ Derate above 25℃ Total Power Dissipation @ TA = 25℃ (1) |
PD |
90 0.6 3.0 |
Watts W/℃ Watts |
| Operating and Storage Temperature Range |
TJ, Tstg |
– 55 to 175 |
℃ |
| Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25℃ (VDD = 25 Vdc, VGS =5Vdc, Peak IL = 30 Apk, L = 0.342 mH, RG = 25 Ω) |
EAS |
145 |
mJ |
| Thermal Resistance — Junction to Case — Junction to Ambient — Junction to Ambient (1) |
RθJC RθJA RθJA |
1.67 62.5 50 |
℃/W |
| Maximum Lead Temperature for Soldering Purposes, 1/8"from case for 10 seconds |
TL |
260 |
℃ |
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
资料整理：维库电子开发网（www.weeqoo.com），的芯片PDF资料基地。
MTB30N06VL的产品描述：
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E–FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.